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AxC1271/README.md

Hi, I'm Andrew!

💻 Computer Engineer Documenting my Projects/Learning
🧑‍🎓 Incoming UCLA MS ECE Student Specializing in VLSI
⚙️ Studying front-end digital VLSI, interested in analog VLSI
📟 Skilled in RTL scripting and FPGA toolchains

My interests are coding, badminton, rock climbing, and baking! Outside of academics, you can catch me skateboarding around campus, playing chess, doodling, or sleeping. :)

💻 Tech Stack:

TypeScript C Python Docker PlatformIO Raspberry Pi AMD nVIDIA

📊 GitHub Stats:



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  1. RISCV-v2 RISCV-v2 Public

    This processor is a more complex pipelined processor building on a previous RISCV-CPU GitHub repository in SystemVerilog, but adds an external bootloader for serial programming via UART with proper…

    SystemVerilog 1

  2. ICStack ICStack Public

    This is a Leetcode-inspired website that aims to provide interview questions for Verilog/RTL design roles for computer engineering students, designed using React/Vite and Firebase.

    TypeScript 1

  3. Verilyzer Verilyzer Public

    This is a fun and self-learning project exploring compiler design using Bison/Flex to compile and simulate Verilog circuits in C/C++.

    C 1

  4. TinyPong TinyPong Public

    This is a TinyTapeout submission (TT-Sky25b) of a simple single-player Pong game written in Verilog as an addition to my original VGA Pong project. The final project is then fabbed onto a physical …

    Verilog 1

  5. RISCV-CPU RISCV-CPU Public

    This is a RTL approach to implementing a simple RISC-V processor using VHDL and the Basys3 FPGA board. Fully synthesizable with instructions to run a simple Fibonacci sequence.

    VHDL 1